Senior ASIC / So C Network-on-Chip Design Engineer or Senior ASIC Design Engineer

Job Description Senior ASIC / So C Network-on-Chip Design Engineer Responsibilities • Design high-performance, high-bandwidth Network-on-Chip (No C) IP for advanced AI So Cs. • Define microarchitecture specifications and develop synthesizable RTL using Verilog/System Verilog. • Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization. • Integrate IP across So C subsystems and support post-silicon debug. • Collaborate with architecture, verification, physical design, and So C integration teams. • Develop Python scripts for design automation and productivity. Qualifications • 8+ years delivering ASIC/So C IP designs. • 6+ years of hands-on digital design, RTL, and microarchitecture experience. • Strong experience with Verilog/System Verilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs. • Experience with No C/interconnect and high-throughput/low-latency designs. • Experience with So C integration, post-silicon debug, and Python scripting. Key Skills: ASIC | No C | RTL | System Verilog | Microarchitecture | CDC | Lint | Synthesis | Timing | PPA | Python